अमूर्त

VLSI Implementation of Soft Bit Flipping Decoder for Geometric LDPC Codes

A.Sushilkumar Singh, K. Jyothi

As the Technology improves digital systems are become more prominent and the reliability and security of memories are essential considerations. As technology scales, memory devices become larger and more eminent error correction codes are required to protect memories from soft errors. Low Density Parity Check (LDPC) Codes are the class of linear block codes which provide large collection of data transmission channels while simultaneously feasible for implementable decoders.One specific type of LDPC codes, namely EG- LDPC are used due to their fault secure detection capability, higher reliability and lower area overhead.In this paper, a low-complexity high-performance algorithm is introduced for decoding of LDPC codes.The developed soft-bit-flipping (SBF) algorithm having advantages of bit-flipping (BF) algorithm and reliability of improve error performance. A hybrid decoding scheme comprised of the BF and SBF algorithms is also proposed to shorten the decoding time.