अमूर्त

VLSI Implementation of Evolvable PID Controller

K.Subbulakshmi

It is known that the application of PID controller span from small industry to high technology industry. Due to PID controllers' widespread use in industry, tuning procedures for them are always a topic of interest. In this dissertation, it is proposed that the controller be tuned using the Genetic Algorithm technique. Using genetic algorithms to perform the tuning of the controller will result in the optimum controller being evaluated for the system every time. For this study, the model selected is a fault tolerant system. The PID controller of the model will be designed using the classical method and the results analyzed. The same model will be redesigned using the GA method. The results of both designs will be compared, analyzed and conclusion will be drawn out of the simulation made. Then the optimized Proportional-Integral- Derivative (PID)Controller is evolved using Field Programmable Gate Array (FPGA)technology. The algorithm is implemented usingDistributed Arithmetic (DA)-based scheme where a Look-Up-Table (LUT) mechanism inside the FPGA is utilized. Twonovel DA-based PID controllers have been proposed for FPGAimplementation. The implementation results show that, the twoDA methods require 13% and 4% of logic devices, respectively,compared to the design using multipliers. Furthermore, thepower consumption is reduced by about 40%. A design whichis efficient in terms of power consumption and chip areawhile having adequate speed means that the FPGA chip canbe used to accommodate more controllers with low powerconsumption, resulting in a cost reduction of the controllerhardware.