Adarsh Kumar Sahu, Vipin Gupta
The demand for high-speed data throughput and high interconnection densities in high-end computing systems due to recent explosive increase in data traffic on the Internet is rapidly growing. In regard to next-generation high-end computing systems, a data transmission speed of over 20 Gb/s is believed. However, the CMOS transimpedance amplifiers technology can be used in fiber-optic applications that require high data rate transmission would benefit from utilizing high-speed analogue front-end components for improving bandwidth and Group delay of transimpedance over the 130nm technology. A simple approach in this paper is to enhance the bandwidth of TIA architecture to improve the group delay variation and power consumption using multistage bandwidth-enhancement circuit techniques over the 130nm CMOS technology. The different-different improvement in TIA architectures such as RGC, RTRN network, nested feedback, are studied in detail and simulated to improve the frequency response of the TIA.