अमूर्त

Test Pattern Generator (TPG) for Low Power Logic Built In Self Test (BIST )

Sabir Hussain K Padma Priya

This research article proposed a logic BIST using linear feedback shift register (LFSR) to generate low power test patterns; It reduced the number of transitions at the input of the circuit-under-test using bit swapping technique. The designed architecture is programmed using Verilog HDL and simulated using CADENCE EDA Tool of 180 nm technology and also proposed design gives better performance in term of power dissipation as compared to standard LFSR.