अमूर्त

TEST PATTERN GENERATION USING PSEUDORANDOM BIST

GaneshBabu.J , Radhika.P

Pseudorandom built-in self test (BIST) generators have been widely utilized to test integrated circuit and systems. In this Project an accumulator-based-3 weight test pattern generation scheme is presented and proposed scheme generates set of test patterns with weights 0, 0.5 and 1. These accumulators are mostly found in current VLSI chips and that the scheme can be efficiently to drive the hardware of BIST pattern generation. The hardware requirements for this project are FPGA SPARTAN 3 and the software which are used as Modelsim and Xilinx . Finally test patterns are produced for 5bit and c880 testbench circuits.