अमूर्त

Survey on Compiler Analysis in India

Amruta Salunkhe, Prof.R.D.Bharati

The key problem in achieving parallelism for distributed memory computers is data distribution, and achieving parallelism and load balancing. Data access latency, a limiting factor in the performance of distributed system, grows significantly with the number of cores in non-uniform cache architectures with distributed cache banks. Many different techniques and algorithms have been proposed or implemented for different programming environments, architectures and applications. However, there is little uniformity, common models, or approach to classifying and comparing such techniques and algorithms. This paper provides an overview of distributed system and how compiler based approach can be used to maximum data access locality and determine an optimize data placement.