अमूर्त

STDN based New Architecture for Power Network in 3D IC?s

Mallikarjun.P.Y , Dr.Y.S.Kumarswamy

In order to reduce the length of global interconnection in 3D IC, Through Silicon via (TSV) provides an exact solution by providing high vertical interconnection density between device dies. TSV has some design issues such as IR drop, thermal dissipation, current delivery per package pin and several voltage domains among dies. To solve these issues, power network designs are used in 3D IC’s which plays an important role. We are going to propose a new integrated architecture of stacked-TSV and power distributed network [STDN]. This architecture provides three major roles such as power network to deliver larger current and reduce IR drop, Thermal network to reduce temperature and decoupling capacitor network to reduce power noise. Along with these roles, it also helps to overcome the limitation of the number of IO power pins. This STDN architecture is used for both single and multiple power domains to obtain good performance in 3D floor plan, IR drop, power noise, temperature, area and also the total length of signal connections for selected Microelectronics Centre of North Carolina[MCNC] benchmarks which can be simulated by using SPICE.