अमूर्त

Static Power Reduction Using Reconfigurable Multi-Mode VTCMOS Switches

B. Munilakshmi, B.Ravi kumar, V.Keerthy Rai

a power-gating scheme was presented to support multiple power-off modes and reduce the leakage power during short periods of inactivity. However, this scheme can suffer from high sensitivity to process variations, which impedes manufacturability. Recently, a new power-gating technique that is tolerant to process variations and scalable to more than two intermediate power-off modes. However this scheme can suffer from Increase in the lower threshold voltage, devices leads increased sub threshold leakage and hence more standby power consumption. We propose body biasing technique used to reduce the power. The proposed design requires less design effort and offers greater power reduction and smaller area cost than the previous method. In addition, it can be combined with existing techniques to offer further static power reduction benefits. Analysis and extensive simulation results demonstrate the effectiveness of the proposed design.