अमूर्त

Reversible Gate Based Testable Sequential Circuits

K.Rekha swathi sri, M.Mano, G.Selvapriya

Testing of Sequential circuits can be done by two test vectors (all 1’s and all 0’s) if the circuits were based on the conservative logic. The circuit is made to be tested by designing the circuit with the help of Reversible logic gates. Fredkin gate is used as reversible gate in this literature. Sequential circuits such as latches, flip flops are designed with the help of conservative logic reversible gate which are coded by modelsim and simulated in this paper. So, testing does not require any scan path access to the internal memory cell, since only normal mode and test mode are required for testing by all zeros and all ones. The objective of this paper is to reduce the number of test vector thereby testing time can be reduced. Thereby Fault coverage is achieved.