अमूर्त

Reliable Low Power CMOS Image Sensor with On-Chip Image Compression and Encryption with FPGA Implementation

Rajesh Kumar. S, Prasath Kumar. S, Usha. P

The majority of digital image processing featuring JPEG image compression uses on-chip image processing circuits for JPEG computations. For these computations, the JPEG algorithm employs the traditional method of computing the discrete cosine transform(DCT).These methods operate with multiplications, which leads to a moderate level of computational complexity. In proposed, we describe an entirely new approach that uses a novel signal processing algorithm namely arithmetic Fourier transform(AFT) for computing the DCT. This new method requires only additions which makes the computation much more efficient and low power. Before compression of image, the image is freed from salt and pepper noise,with the help of median filter.This further describes an encryption technique using Advance Encryption Standard (AES). The security offered by AES algorithm is unbreakable. This resists all the known types of attacks. The architecture and circuits may be implemented in a conventional CMOS process.