अमूर्त

Reduction of Standby Leakage Power in CMOS VLSI Systems

Hari. S

In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in CMOS very large scale integration (VLSI) systems by generating the adaptive optimal reverse body-bias voltage. In order to minimize the leakage power dissipation, several circuit techniques have been proposed, such as multi-threshold voltage CMOS (MTCMOS) and variable threshold voltage CMOS (VTCMOS) using variable substrate bias voltage. The adaptive optimal body-bias voltage is generated from the proposed leakage monitoring circuit, which compares the sub threshold current (ISUB) and the band-to-band tunnelling current (IBTBT). The proposed circuit was simulated in MICROWIND using a 32-nm bulk CMOS technology and evaluated further. The proposed approach demonstrates that the optimal body bias reduces a considerable amount of standby leakage power dissipation in CMOS integrated circuits. In this approach, the temperature and supply voltage variations are compensated by the proposed feedback loop.