अमूर्त

Reduction of Delay and Power by Using MLDD Technique in Error Correction

S.Abinaya, Mr.M.Yuvaraja

This project presents an error-detection method for Euclidean Geometry Low Density Parity Check codes with majority logic decoding methodology .The algorithm is synthesized in Xilinx 12.1 and simulated using Modelsim 5.7g .Majority logic decodable codes are suitable for memory applications due to their capability to correct a large number of errors. However, they require a large decoding time that impacts memory performance. The proposed fault-detection method significantly reduces the delay time by detecting the errors in parallel and in pipelining manner. Also the memory access time reduces when there is no error in the data read. The technique uses the majority logic decoder itself to detect failures, which makes the area overhead minimal and keeps the extra power consumption low. Starting from the original design of the ML decoder introduced, the proposed ML Detector/Decoder (MLDD) has been implemented.