अमूर्त

Power Optimization Using Clock Gating Technique

R.Saranya, K.Radhika , Dr.S.Nirmala, K.Priyameenkshi

Multithreshold CMOS is very effective for reducing standby leakage power during long periods of inactivity. Recently, a power-gating scheme to support multiple poweroff modes and reduce the leakage power during short periods of inactivity. This scheme is highly sensitive to process variations. Therefore,we propose a clock gating technique that is tolerant to process variations and scalable to more than two intermediate power-off modes. The clock gating improves the design architecture and reduces the delay, area and power consumption. In addition, it can be combined with existing techniques to offer further static power reduction benefits. The analysis and simulation results demonstrate the effectiveness of the proposed design.