अमूर्त

Power Efficient Enhancement Technique for Flip- Flop Design

S. Sathyapriya

Low power pulse triggered flip-flop is designed in this paper. In the pulse generation control logic, AND function is removed and a simple two – transistor AND gate design is used to reduce complexity and to facilitate a faster discharge operation. A pulse enhancement technique is applied to speed up the discharge along the critical path when needed. In resultant circuit, transistor size in the delay inverter and pulse generator circuit is reduced for power saving. Various post layout simulation results based on UMC CMOS 90-nm technology reveal that the proposed design features the best power-delay-product performance in seven FF designs under comparison. Its maximum power saving against existing design is up to 38.4%. Compared with the conventional transmission gatebased FF design, the average leakage power consumption is also reduced by a factor of 3.52.