अमूर्त

Performance Analysis of Positive Feedback Adiabatic Logic for Low Power

Tanuja Jaggi, Ravinder Kumar

This paper present ultra low power comparator based on new adiabatic technique recently come under investigation. Low power design is becoming extremely important for high performance digital system such as microprocessor and other applications. This switching logic reduces the power dissipation by reusing the energy drawn from the power supply. We introduced single bit comparator designed by proposed adiabatic technique and compared with static cmos and positive feedback adiabatic logic on the basis of transistor count to implement them and average power consumption with different values of input frequencies. The simulation is performed with SPICE using 180nm cmos technology which results proposed logic can save power dissipation compared with static cmos logic and PFAL at different frequencies.