अमूर्त

Optimization and Power Reduction of Built-In Repair Analyzer for Memories

S.Jeevitha, T.Angala Parameshwari, R.Yamini

Due to the large die size and the complex fabrication process for combining memories and logic, system-on-chip suffer from relatively lower yield, necessitating yield optimization techniques. The area occupied by the embedded memories takes more than half of the total area of a typical SoC, and the ratio is expected to keep increasing in the future. Therefore, the overall SoC yield is dominated by the memory yield, and optimizing the memory yield plays a crucial role in the SoC environment. To improve the yield, memory arrays are usually equipped with spare elements. The infrastructure that provides the optimal repair rate with a single test is performed and response of the test denotes the fault address and it is stored. The final analysis to find a solution is performed on the stored fault addresses. Error detection is based syndrome storing-based detection method, which involves evaluation of consecutive code syndromes at the receiver. Power consumption is more during test mode than in normal mode. Inorder to reduce power, bit transitions in test pattern generation is reduced by use of Bit- Swapping Linear Feedback Shift Register leading to power reduction.