अमूर्त

One Bit-Line Multi-Threshold SRAM Cell With High Read Stability

Prangya Parimita Nanda , Kanan Bala Ray, Sushree Sangita Das

Memory are inherent part of the nearly all of the digital models and so minimization of power usage of a memory is major role in upgrading the system efficiency, performance reliability. In the paper new multi-threshold one bit-line SRAM cell is proposed , for both read and write operation one bit-line is used. Minimization of power usage because of one bit-line usage and more read stability than conventional multi threshold SRAM cell. In between the proposed multi-threshold one bit-line SRAM cell and conventional multi-threshold SRAM cell comparison will be held in terms of power usage, SNM, delay. The proposed multi-threshold one bit-line SRAM cell usage 94.6% reduction in power in write 1 operation, 93.1% reduction in power in read 1 operation than multi-threshold SRAM. We drawn the schematics using virtuoso ADE of cadence ,and all simulation data are taken out using cadence spectre analyzer with 45nm technology library at 1.8v.