अमूर्त

Offset Reduction of CMOS Based Dynamic Comparator by using Charge Storage Techniques - A Comparative Study

Neerav Mehan, Anshul Kumar, Kamna Kohli, Neha Sharma

Comparator is one of the most widely used building block for analog and mixed signal systems. For the implementation of high-performance CMOS A/D converters, low offset comparators are essential. In this paper, dynamic comparator offset is calculated to the extent of high accuracy. The offset so calculated has been reduced by the charge storage techniques to achieve an efficient design. In addition to the offset, propagation delay and power dissipation, being the important parameter of the comparator, has been analyzed. It is observed that offset voltage in the comparator has been reduced to 350μV for output offset storage technique and 400μV for input offset storage techniques from 91mV. In this paper, BPTM model has been used in analyze the dynamic comparator.