अमूर्त

Low Power Multi Bit Flip Flops Design for VLSI Circuits

L.Ange Prabha, S.Joy

In this paper we present a power optimization technique to reduce clock power by using multi bit flip flop method. We have proposed the several techniques to overcome the problems of flip- flops replacement without timing and placement capacity constraints violation. First we perform the co –ordinate transformation to convert the diamond shape legal region into rectangular region and Building the Combination table to identify the Mergeable Flip-flops’ Moreover, by judiciously merging and placing the MBFFs, the total wire length is also significantly reduced.