अमूर्त

Leakage Power Reduction for Logic Circuits Using Variable Body Biasing Technique

Anjana R and Ajay K Somkuwar

The leakage power dissipation has become one of the most dominant factors in total power consumption and yet a challenge for the VLSI designers as it doubles every two years according to Moore’s law According to ITRS, leakage power consumption may dominate total power consumption [1]. By scaling down the threshold voltage, remarkable reduction in leakage in leakage power can be obtained. We propose a new leakage reduction technique, named “variable body biased keeper”, which can be applied to general logic circuits as well as memory. Our SSVBB approach retains the logic state while saving the leakage power. Like conventional approach, our approach can employ dual Vth technologies reducing leakage power with the area and delay overhead.