अमूर्त

Implementation of Split Radix Algorithm for 12-Point FFT & IFFT

P.Malyadri, D.Jayanayudu, G.Mahendra

Discrete Fourier transform (DFT) is widespread used in many fields of science and engineering. DFT is implemented with efficient algorithms categorized as Fast Fourier Transform. A fast algorithm is proposed for computing a length-N=6m DFT. The proposed algorithm is a blend of radix-3 and radix-6 FFT. It is 2rx3m variant of split radix and can be flexibly implemented a length DFT. Novel order permutation of sub-DFTs and reduction of the number of arithmetic operations enhance the practicability of the proposed algorithm. It inherently provides a wider choice of accessible FFT’s lengths. The proposed algorithm shows that its implementation requires less real operations as compared with the published algorithms. The pending update to system Verilog contains several new packages and functions. The new packages include support for both fixed-point and floating-point binary math. These fully Non-synthesizable packages will raise the level of abstraction in System Verilog. DSP applications, which previously needed an independent processor core, or required very difficult manual translation, can now be performed within your system Verilog source code. In addition, Schematic-based DSP algorithms can now be translated directly to System Verilog.