B. Doss, K.Soundararajan, Y. Narasimha Murthy
This paper presents a revolutionary pipelined architecture for constant power and low-area implementation of adaptive FIR filter which uses the concept of Distributed Arithmetic (DA). Area efficiency can further be improved by using Offset Binary Coding in this filter design. With this improvement, the LUT structure can be reduced to a 4-delay element structure. Along with this, DA based inner product computations are done by using conditional carry-save accumulation instead of the normal adder based shift accumulation. The proposed structure will result in a much area efficient filter structure compared to the existing design.