अमूर्त

High Speed Vedic Multiplier Using Nikhilam Sutra with Barrel Shifter

L Kishore Kumar Reddy, M Venkata Subbaiah

Multiplication is one of the most important operation in computer arithmetic. Many integer operations such as multiplication, squaring, division and computing reciprocal require same order of time as multiplication .This paper describes the implementation of an 64-bit Vedic multiplier enhanced in terms of propagation delay when compared with conventional multiplier like array multiplier, Braun multiplier, modified booth multiplier and Wallace tree multiplier. In our design we have utilized a barrel shifter which requires only one clock cycle for ‘n’ number of shifts. The propagation delay comparison was extracted from the synthesis report and static timing report as well.