अमूर्त

FPGA-Based Bit Error Rate Performance measuring of Wireless Systems

Viha Pataskar , Vishal Puranik

The bit error ratio (also BER) is the number of bit errors divided by the total number of transferred bits during a studied time interval. The proposed BER tester (BERT) integrates fundamental baseband signal processing modules of a typical wireless communication system along with a realistic fading channel simulator and an accurate Gaussian noise generator onto a single FPGA to provide an accelerated and repeatable test environment. Using a developed graphical user interface, the error rate performance of single- and multiple-antenna systems over a wide range of parameters can be rapidly evaluated. The FPGA-based BERT should reduce the need for time-consuming software based simulations, hence increasing the productivity. The BERT modules were developed using deviceindependent HDL, and no specific features of the FPGAs, such as built-in soft processors, were utilized. Therefore, the system is portable and can easily be synthesized onto larger and faster new FPGAs for the rapid prototyping of increasingly complex emerging wireless communication systems. FPGA solutions offer significant cost reduction compared to commercially available solutions.