अमूर्त

Designing of MIPS R2000 Processor on spartan3E

Sanghita Deb, Supriya Sarkar , G. Dilip , Tejaswini R. Choudri

In this paper, we analyze the Processor designed in this project was based on the MIPS R2000. The Objective of the design is to run all Instructions in One cycle. It uses the separate Harvard architecture, it increase the speed of processor. Previews RISK MIPS pipeline design consists 3stage pipeline design, but MIPS R2000 consists 5stage design. MIPS R2000 modules are implemented by pipeline and simulated successfully on Xilinx ise.