अमूर्त

Design of Low Power Counters Using Reversible Logic

Asima Jamal, Jai Prakash Prasad

In today’s world, the complexity of the chip is increasing as more and more devices are being connected on a single chip. Due to the high density of the chip, the power dissipation increases demanding better power optimization methods. One of the methods to achieve power optimization is by using reversible logic. It can be used in low power CMOS designs, quantum computing, nanotechnology and optical computing. This paper presents an optimized sixteen-bit binary sequential counter based on reversible logic using Feynman, and Fredkin gates. Optimization of the sequential circuit is achieved on the basis of total number of gates used in the circuit and total number of garbage outputs generated. Circuits have been designed using Cadence Virtuoso Schematic Editor