अमूर्त

Design of Low Power Aging Aware Multiplier Using Adaptive Hold Logic.

K.Raveena Shree, M.Ragavi, M.Udhayavani.

Digital multipliers are among the most arithmetic functional units in many applications, such as Fourier transform, discrete cosine transforms, and digital filtering. These applications depends on multipliers, if the multipliers are slow, the performance of entire circuits will be reduced. The proposed aging-aware multiplier design is implemented with a novel adaptive hold logic (AHL) circuit. The multiplier is based on variable-latency technique and adjust the AHL circuit to achieve reliable operation using NBTI and PBTI effects The AHL circuit can decide the input patterns require one or two cycles to adjust the judging criteria to ensure the minimum performance degradation after considerable aging occurs. Comprehensive analysis and comparison of the multipliers performance under different cycle periods to show the effectiveness of our proposed architecture. The performance in 16- and 32-bit multipliers, can be easily extended to large designs. It can provide reliable operations even after the aging effect occurs. The Razor flip-flops detect the timing violations and re-execute the operations using two cycles. The architecture will adjust the percentage of one-cycle patterns to minimize performance degradation due to the aging effect. When the circuit is aged, and many errors occur, the AHL circuit uses the second judging block to decide if an input is one or two cycles. The multiplier is adjust the AHL to mitigate performance degradation due to increase delay.