अमूर्त

Design of Cache Memory with Cache Controller Using VHDL

Yogesh S. Watile, A. S. Khobragade

We report on the design of efficient cache controller suitable for use in FPGA-based processors. Semiconductor memory which can operate at speeds comparable with the operation of the processor exists; it is not economical to provide all the main memory with very high speed semiconductor memory. The problem can be alleviated by introducing a small block of high speed memory called a cache between the main memory and the processor. Set-associative mapping compromise between a fully associative cache and a direct mapped cache, as it increases speed. With reference to set associative cache memory we have designed cache controller. Spatial locality of reference is used for tracking cache miss induced in cache memory. In order to increase speed , less power consumption and tracking of cache miss in 4-way set associative cache memory, FPGA cache controller will proposed by this research work . We believe that our design work achieves less circuit complexity, less power consumption and high speed in terms of FPGA resource usage