Chaitra N, Mr. Praveen Kumar Y G, Dr. M Z Kurian
In this paper, an adaptive FIR filter hardware architecture with high performance is designed. The RLS (Recursive Least Square) algorithm for adaptive signal processing is explored based on QR decomposition, which uses Givens Rotation algorithm. The Givens Rotation algorithm will be implemented using CORDIC algorithm. This design is suitable for high-speed FPGAs or ASIC design. This QR Design is tested using Xilinx-FPGA as a case study