अमूर्त

Design and Analysis of Low-Power 11- Transistor Full Adder

Ravi Tiwari, Khemraj Deshmukh

Full adders are exigent components in applications such as digital signal processors (DSP) architectures and microprocessors. In this paper, we propose a technique to build a new 11-transistor FA .We have done HSPICE simulation runs the new design 11-T full adders .In CMOS integrated circuit design there is a tradeoff between static power consumption and technology scaling. Static power dissipation is a challenge for the circuit designer. So we reduce the static power dissipation. In order to achieve lower static power consumption, one has to scarifies design area and circuit performance. In this paper we propose a new circuit of 11-Transistor full adder in CMOS VLSI circuit