अमूर्त

Asynchronous Data Sampling Within Delay Buffer Using Gated Driver Tree

M.Keerthika, M.Ramya, Assistant Professor S. Udhayakumar

This paper presents circuit design of a low-power delay buffer. The proposed delay buffers are accessed sequentially, and it operates as a ring-counter addressing strategy. A novel gated-clock-driver tree is then applied to further reduce the activity along the clock distribution network. Double-edge-triggered (DET) flip-flops and the C-element gated-clock strategy is implemented in the delay buffer in order to reduce number of clock cycles and the dynamic power consumption. However an asynchronous data sampling is introduced at the output side by incorporating clock gating with DETFFs to further reduce dynamic power consumption, it causes data miscommunication error between clock edges. By implementing G-DETFF technique in the gated driver tree the asynchronous data sampling has been removed and the parameters such as power and area are evaluated.