अमूर्त

ANALYSIS OF SYNTHESIS ISSUES ABOUT DESIGNING DSP DEVICES

Akash Verma, B.S. Rai

This paper discusses the issues related to the synthesizing the designs of DSP devices to FPGA. The high level codes used for synthesis input, are in VHDL. The central issues behind the designs are synthesizable or not are, used HDL libraries and data types. All the issues and solutions are illustrated using 32-Point Fast Fourier Transform. In the beginning, the IEEE fixed point package (fixed_pkg) is used for designing FFT-32 then whole logic is designed using single IEEE package (STD_LOGIC_1164) which is absolutely synthesizable to FPGA. For implementing DSP algorithms using ‘STD_LOGIC_1164’, ‘real type’ data structure is represented by array of bits, that is ‘bit_vector’. Algorithms for real type addition, subtraction and multiplication are developed using array of bits which will fulfill the function of complex and real arithmetic. DSP algorithms implemented through this design method are complete synthesizable and can be implemented with very high degree of precision